#include <c33L05.h>

#define NAND_FLASH_ADDRESS *(volatile u8 *)(0x04000000)

typedef void (*fun)();
typedef s32 (*fun2)(u32, u32);
typedef s32 (*fun3)(u32, u8*);

extern unsigned long __dp;

struct _X {
    u16 a;
    u16 b;
    u32 c;
    u32 d;
    u32 e;
    u32 f;
    u32 g;
};

struct _X DAT_00001278[7] = {
    {0x0073, 0x0000, 0x00000020, 0x00000005, 0x000002c0, 0x00000000, 0x00000000},
    {0x0075, 0x0000, 0x00000020, 0x00000005, 0x000006c0, 0x00000000, 0x00000000},
    {0x0076, 0x0000, 0x00000020, 0x00000005, 0x00000ec0, 0x00000000, 0x00000000},
    {0x0079, 0x0000, 0x00000020, 0x00000005, 0x00001ec0, 0x00000001, 0x00001003},
    {0x0071, 0x0000, 0x00000020, 0x00000005, 0x00003ec0, 0x00000001, 0x00002003},
    {0x00f1, 0x0001, 0x00000100, 0x00000008, 0x000003d8, 0x00000001, 0xffffffff},
    {0x00da, 0x0001, 0x00000100, 0x00000008, 0x000007d8, 0x00000001, 0xffffffff},
};

u32 DAT_00001320;
u32 DAT_00001324;
u8  DAT_00001328 = 1;
u32 DAT_0000132c;
u8  DAT_00001330 = 1;
u8  DAT_00001340;
u32 DAT_00001344;
u8 *DAT_00001348;
u8  DAT_0000134c;
u8  DAT_00001351;
u32 DAT_0000135c;
u8 *DAT_00001360;
fun DAT_0000136c;
fun2 DAT_00001374;
fun3 DAT_0000137c;
u32 DAT_00001388;
u32 DAT_0000138c;
u32 DAT_00001390;
u32 DAT_00001394;
u32 DAT_000013a4;
u32 DAT_000013b4;
u32 DAT_000013c4;
u32 DAT_000013c8;
u32 DAT_000013cc;
u8 *DAT_000013d0;
u32 DAT_000013d4;
u32 DAT_000013d8;
u8  DAT_000013dc;
u8  DAT_000013dd;
u8  DAT_000013de;
u32 DAT_000013e0;
u32 DAT_000013e4;
u32 DAT_000013e8;
u32*DAT_000013f4;
u8  DAT_000013f8;
u8  DAT_000013f9;
u8  DAT_000013fa;
u8  DAT_000013fb;
u32 DAT_00001404;
u8  DAT_00001408;
u8  DAT_00001409;
u32 DAT_0000140c;
u32 DAT_00001410;
u8  DAT_00001414;
u8  DAT_00001415;
u32 DAT_00001418;
u32 DAT_0000141c;
u32 DAT_00001420;
u32 DAT_00001424;
u8  DAT_00001428[0x10];
u32 DAT_00001438;
u32 DAT_0000143c;
u32 DAT_00001440;
u32 DAT_00001444;
u32 DAT_00001448;
u32 DAT_0000144c;
u32 DAT_00001450;
u32 DAT_00001454;
u32 DAT_00001458;
u8  DAT_0000145c[0x10];
u32 DAT_0000146c;
u32 DAT_00001470;

s32 FUN_000002fc(u32 r6);
void FUN_000003ee(u32 r6, u8 *r7);
void FUN_000004a2();
void FUN_000005f2();
void FUN_00000630();
void FUN_00000700();
void FUN_00000712();
u32 FUN_00000736(u8 r6);
s32 FUN_0000077c(u32 r6);
s32 FUN_000007a0(u8 *r6);
s32 FUN_000007cc(u32 r6);
s32 FUN_000008c6(u32 r6, u8 *r7);
s32 FUN_000009a2(u32 r6, u8 *r7);
u32 FUN_00000a48(u8 r6);
s32 FUN_00000a8e(u32 r6);
s32 FUN_00000ab2(u8 *r6);
s32 FUN_00000ade(u32 r6);
s32 FUN_00000b2e(u32 r6, u8 *r7);
s32 FUN_00000bf0(u32 r6, u8 *r7);
u32 FUN_00000c7e(u32 r6);
s32 FUN_00000dfa(u32* r6, u32 r7, u32 r8);
s32 FUN_00000e96();
void FUN_0000113c();
s32 FUN_00001144(u32, u32);

int main()
{
    asm("xld.w %r4,0x3000");
    asm("ld.w %sp,%r4");
    asm("xld.w %r15,__dp");
    FUN_00000700();
    FUN_00000712();
    // K64, BOOT: No pull-up
    CPU_IO.PUPK6H = 0;
    // P54 port extended function: P54
    CPU_IO.EFP54 = 1;
    CPU_IO.IOC54 = 1;
    CPU_IO.P54D = 1;
    FUN_000005f2();
    FUN_00000630();
    FUN_000004a2();
    FUN_0000113c();
    DAT_00001448 = 0x2600000;
    DAT_0000144c = 0;
    DAT_00001450 = 0;
    for (DAT_00001440=0; DAT_00001440<0x200; DAT_00001440++) {
        DAT_00001444 = DAT_00001440*0x200 + DAT_0000144c*0x200 + 0x4000;
        DAT_00001454 = DAT_0000144c + 0x20 + DAT_00001440;
        DAT_00001458 = FUN_00001144(DAT_00001454, DAT_00001448);
        DAT_00001448 += 0x200;
        DAT_00001450++;
        if (DAT_00001450 > 0x17f) {
            break;
        }
    }
    // Trap table base address
    CPU_IO.TBRP = 0x59;
    CPU_IO.TTBR = 0x02600000;
    (*(void (*)())(*(unsigned long *)0x02600000))();
}

s32 FUN_000002fc(u32 r6) {
    CPU_IO.P24D = 1;
    CPU_IO.P51D = 0;
    NAND_FLASH_ADDRESS = 0xff;
    CPU_IO.P24D = 0;
    while (CPU_IO.P26D == 0) {

    }
    CPU_IO.P51D = 1;
    CPU_IO.P24D = 1;
    CPU_IO.P51D = 0;
    NAND_FLASH_ADDRESS = 0x50;
    CPU_IO.P24D = 0;
    CPU_IO.P25D = 1;
    NAND_FLASH_ADDRESS = r6;
    NAND_FLASH_ADDRESS = r6>>9;
    NAND_FLASH_ADDRESS = r6>>17;
    NAND_FLASH_ADDRESS = r6>>25;
    CPU_IO.P25D = 0;
    for (DAT_00001470=0; DAT_00001470<100; DAT_00001470++) {
        asm("nop");
    }
    while (CPU_IO.P26D == 0) {

    }
    for (DAT_0000146c=0; DAT_0000146c<16; DAT_0000146c++) {
        DAT_0000145c[DAT_0000146c] = NAND_FLASH_ADDRESS;
        if (DAT_0000145c[DAT_0000146c] != 0xff) {
            CPU_IO.P51D = 1;
            return 1;
        }
    }
    CPU_IO.P51D = 1;
    return 0;
}

void FUN_000003ee(u32 r6, u8 *r7) {
    CPU_IO.P24D = 1;
    CPU_IO.P51D = 0;
    NAND_FLASH_ADDRESS = 0xff;
    CPU_IO.P24D = 0;
    while (CPU_IO.P26D == 0) {

    }
    CPU_IO.P51D = 1;
    CPU_IO.P24D = 1;
    CPU_IO.P51D = 0;
    NAND_FLASH_ADDRESS = 0x00;
    CPU_IO.P24D = 0;
    CPU_IO.P25D = 1;
    NAND_FLASH_ADDRESS = r6;
    NAND_FLASH_ADDRESS = r6>>9;
    NAND_FLASH_ADDRESS = r6>>17;
    NAND_FLASH_ADDRESS = r6>>25;
    CPU_IO.P25D = 0;
    while (CPU_IO.P26D == 0) {

    }
    for (DAT_0000146c=0; DAT_0000146c<0x200; DAT_0000146c++) {
        r7[DAT_0000146c] = NAND_FLASH_ADDRESS;
    }
    CPU_IO.P51D = 1;
}

void FUN_000004a2() {
    //  Area 6,5,4 internal/external access:  Internal access
    CPU_IO.A5IO = 1;
    CPU_IO.A6IO = 1;
    // #CE pin function selection: #CE7/8..#CE17/18
    CPU_IO.CEFUNC = 2;
    // #WAIT enable: Enabled
    CPU_IO.SWAITE = 1;
    // External interface method selection: #BSL
    CPU_IO.SBUSST = 1;
    // A0/#BSL mode select:  #BSL mode
    CPU_IO.WRPROT = 0x96;
    CPU_IO.BSLSEL = 1;
    // Bus clock generator enable: Enabled
    CPU_IO.WRPROT = 0x96;
    CPU_IO.BCLGEN = 1;
    // BCLK output control: Fixed at H
    CPU_IO.RBCLK = 1;
    //  PA2,PA1,PA0 port extended function: PA2,#SDRAS,#SDCAS
    CPU_IO.FPA0 = 2;
    CPU_IO.FPA1 = 2;
    CPU_IO.FPA2 = 1;
    // P30 function selection: #WAIT #CE4/#CE5
    CPU_IO.CFP30 = 1;
    // P21,P20 port extended function: #SDWE,SDCKE
    CPU_IO.EFP20 = 1;
    CPU_IO.EFP21 = 1;
    // P63,P62,P61,P60 port extended function: UDQM,LDQM,SDA10,SDCLK
    CPU_IO.EFP60 = 3;
    CPU_IO.EFP61 = 1;
    CPU_IO.EFP62 = 1;
    CPU_IO.EFP63 = 1;
    // P53 port extended function: #SDCE
    CPU_IO.EFP53 = 2;
    for (DAT_00001470=0; DAT_00001470<1000; DAT_00001470++) {
        
    }
    // SDRAM auto-refresh counter: 0x177
    CPU_IO.AURCO = 0x177;
    // SDRAM self-refresh counter: 0xf
    CPU_IO.SELCO = 0xf;
    // SDRAM self-refresh enable: Enabled
    CPU_IO.SELEN = 1;
    // SDRAM tRC, tRFC and tXSR cycles: 3 cycles
    // SDRAM tRP and tRCD cycles: 1 cycle
    CPU_IO.us_SDRAM_INIT = 2;
    // SDRAM address configuration: 4M x 16 bits x 1
    CPU_IO.ADDRC = 1;
    // SDRAM controller enable: Enabled
    CPU_IO.SDON = 1;
    // SDRAM initialize flag != Initialized
    while (CPU_IO.SDEN != 1) {
        // PRE trigger: Trigger
        CPU_IO.INIPRE = 1;
        for (DAT_00001470=0; DAT_00001470<2; DAT_00001470++) {
            
        }
        for (DAT_00001470=0; DAT_00001470<8; DAT_00001470++) {
            // REF trigger: Trigger
            CPU_IO.INIREF = 1;
        }
        for (DAT_00001470=0; DAT_00001470<2; DAT_00001470++) {
            
        }
        // MRS trigger: Trigger
        CPU_IO.INIMRS = 1;
        for (DAT_00001470=0; DAT_00001470<2; DAT_00001470++) {
            
        }
    }
    // SDRAM high-performance access: High perform
    // Area 8/14,7/13 configuration: SDRAM. 0x2000000~0x3FFFFFF, 16MB*2
    // Instruction queue buffer enable: Enabled
    CPU_IO.us_SDRAM_CFG = 0xf;
}

void FUN_000005f2() {
    // Area 6 internal/external access:  Internal access
    CPU_IO.A6IO = 1;
    // P24,P25: Output
    CPU_IO.IOC24 = 1;
    CPU_IO.IOC25 = 1;
    CPU_IO.P51D = 1;
    // P51 Output
    CPU_IO.IOC51 = 1;
    // P35,P34 port extended function:  #SMRE,#SMWE
    CPU_IO.EFP34 = 1;
    CPU_IO.EFP35 = 1;
    // P51 port extended function: P51
    CPU_IO.EFP51 = 1;
    // Booting code enable: Enabled
    CPU_IO.SMCODE = 1;
}

void FUN_00000630() {
    CPU_IO.P54D = 1;
    CPU_IO.IOC54 = 1;
    // P54 port extended function: P54
    CPU_IO.EFP54 = 1;
    CPU_IO.P42D = 0;
    // P42 port extended function: P42
    CPU_IO.EFP42 = 1;
    CPU_IO.IOC42 = 1;
    CPU_IO.P50D = 1;
    CPU_IO.IOC50 = 1;
    // P50 port extended function: P50
    CPU_IO.EFP50 = 1;
    CPU_IO.P52D = 0;
    CPU_IO.IOC52 = 1;
    // P52 port extended function: P52
    CPU_IO.EFP52 = 1;
    CPU_IO.P41D = 1;
    CPU_IO.P40D = 1;
    // P40 port extended function: P40
    CPU_IO.EFP40 = 1;
    // P41 port extended function: P41
    CPU_IO.EFP41 = 1;
    CPU_IO.IOC40 = 1;
    CPU_IO.IOC41 = 1;
    // P03 port extended function: P03/#SRDY0
    CPU_IO.EFP03 = 0;
    // P03 function selection: P03
    CPU_IO.CFP03 = 0;
    CPU_IO.IOC03 = 0;
    CPU_IO.P42D = 0;
    CPU_IO.P40D = 0;
    CPU_IO.P41D = 0;
    // P33,P32,P31 port extended function:  SDI,P32, etc.,P31, etc.
    CPU_IO.us_EFP3 = 0x40;
    // P33,P32,P31 function selection: P33,P32,P31
    CPU_IO.CFP31 = 0;
    CPU_IO.CFP32 = 0;
    CPU_IO.CFP33 = 0;
    // P31 port extended function: P31, etc.
    CPU_IO.CFEX3 = 0;
    CPU_IO.P31D = 0;
    CPU_IO.P32D = 0;
    CPU_IO.IOC31 = 1;
    CPU_IO.IOC32 = 1;
    // #CE10EX–#CE4 (P55–P50) pull-up: No pull-up
    CPU_IO.PUPCE = 0;
}

// P23 Output Low
void FUN_00000700() {
    // P23 function selection: P23
    CPU_IO.CFP23 = 0;
    CPU_IO.IOC23 = 1;
    CPU_IO.P23D = 0;
}

// P02 Output Low
void FUN_00000712() {
    // P02 function selection: P02
    CPU_IO.CFP02 = 0;
    // P02 port extended function: P02/#SCLK0
    CPU_IO.EFP02 = 0;
    CPU_IO.IOC02 = 1;
    CPU_IO.P02D = 0;
}

u32 FUN_00000736(u8 r6) {
    DAT_00001324 = 0;
    for (DAT_00001328=0x01; DAT_00001328!=0; DAT_00001328<<=1) {
        if (DAT_00001328&r6 == 0) {
            DAT_00001324++;
        }
    }
    return DAT_00001324;
}

s32 FUN_0000077c(u32 r6) {
    while (r6--) {
        if (CPU_IO.P26D == 1) {
            break;
        }
    }
    if (r6) {
        return 0;
    }
    return -1;
}

s32 FUN_000007a0(u8 *r6) {
    if (CPU_IO.P26D == 0) {
        return -1;
    }
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0x70;
    CPU_IO.P24D = 0;
    *r6 = NAND_FLASH_ADDRESS;
    return 0;
}

s32 FUN_000007cc(u32 r6) {
    CPU_IO.P51D = 0;
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0x00;
    CPU_IO.P24D = 0;
    CPU_IO.P25D = 1;
    NAND_FLASH_ADDRESS = 0x00;
    NAND_FLASH_ADDRESS = 0x08;
    NAND_FLASH_ADDRESS = r6<<6;
    NAND_FLASH_ADDRESS = r6>>2;
    NAND_FLASH_ADDRESS = r6>>10;
    CPU_IO.P25D = 0;
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0x30;
    CPU_IO.P24D = 0;
    if (FUN_0000077c(600) == -1) {
        CPU_IO.P51D = 1;
        return -1;
    }
    DAT_00001340 = NAND_FLASH_ADDRESS;
    if (FUN_00000736(DAT_00001340) <= 1) {
        CPU_IO.P24D = 1;
        NAND_FLASH_ADDRESS = 0x00;
        CPU_IO.P24D = 0;
        CPU_IO.P25D = 1;
        NAND_FLASH_ADDRESS = 0x00;
        NAND_FLASH_ADDRESS = 0x08;
        NAND_FLASH_ADDRESS = (r6<<6)|0x01;
        NAND_FLASH_ADDRESS = r6>>2;
        NAND_FLASH_ADDRESS = r6>>10;
        CPU_IO.P25D = 0;
        CPU_IO.P24D = 1;
        NAND_FLASH_ADDRESS = 0x30;
        CPU_IO.P24D = 0;
        if (FUN_0000077c(600) != -1) {
            DAT_00001340 = NAND_FLASH_ADDRESS;
            CPU_IO.P51D = 1;
            if (FUN_00000736(DAT_00001340) <= 1) {
                return 0;
            }
            return -1;
        }
    }
    CPU_IO.P51D = 1;
    return -1;
}

s32 FUN_000008c6(u32 r6, u8 *r7) {
    DAT_00001348 = r7;
    CPU_IO.P51D = 0;
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0x00;
    CPU_IO.P24D = 0;
    CPU_IO.P25D = 1;
    NAND_FLASH_ADDRESS = 0x00;
    NAND_FLASH_ADDRESS = (r6&0x03)<<1;
    NAND_FLASH_ADDRESS = r6>>2;
    NAND_FLASH_ADDRESS = r6>>10;
    NAND_FLASH_ADDRESS = r6>>18;
    CPU_IO.P25D = 0;
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0x30;
    CPU_IO.P24D = 0;
    if (FUN_0000077c(600) == -1) {
        CPU_IO.P51D = 1;
        return -1;
    }
    // ECC circuit reset: Reset
    CPU_IO.ECCRST = 1;
    // ECC circuit enable: Enabled
    CPU_IO.ECCEN = 1;
    for (DAT_00001344=0x200; DAT_00001344!=0; DAT_00001344--) {
        *DAT_00001348++ = NAND_FLASH_ADDRESS;
    }
    // ECC circuit enable: Disabled
    CPU_IO.ECCEN = 0;
    CPU_IO.P51D = 1;
    DAT_00001344 = 29999;
    // Parity data ready status == Busy
    while (CPU_IO.ECCRDY == 0) {
        DAT_00001344--;
        if (DAT_00001344 == 0x00) {
            return -1;
        }
    }
    return 0;
}

s32 FUN_000009a2(u32 r6, u8 *r7) {
    DAT_00001348 = r7;
    CPU_IO.P51D = 0;
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0x00;
    CPU_IO.P24D = 0;
    CPU_IO.P25D = 1;
    NAND_FLASH_ADDRESS = (r6&0x03)<<4;
    NAND_FLASH_ADDRESS = 0x08;
    NAND_FLASH_ADDRESS = r6>>2;
    NAND_FLASH_ADDRESS = r6>>10;
    NAND_FLASH_ADDRESS = r6>>18;
    CPU_IO.P25D = 0;
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0x30;
    CPU_IO.P24D = 0;
    if (FUN_0000077c(600) == -1) {
        CPU_IO.P51D = 1;
        return -1;
    }
    for (DAT_00001344=0x10; DAT_00001344!=0; DAT_00001344--) {
        *DAT_00001348++ = NAND_FLASH_ADDRESS;
    }
    CPU_IO.P51D = 1;
    return 0;
}

u32 FUN_00000a48(u8 r6) {
    DAT_0000132c = 0;
    for (DAT_00001330=0x01; DAT_00001330!=0; DAT_00001330<<=1) {
        if (DAT_00001330&r6 == 0) {
            DAT_0000132c++;
        }
    }
    return DAT_0000132c;
}

s32 FUN_00000a8e(u32 r6) {
    while (r6--) {
        if (CPU_IO.P26D == 1) {
            break;
        }
    }
    if (r6) {
        return 0;
    }
    return -1;
}

s32 FUN_00000ab2(u8 *r6) {
    if (CPU_IO.P26D == 0) {
        return -1;
    }
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0x70;
    CPU_IO.P24D = 0;
    *r6 = NAND_FLASH_ADDRESS;
    return 0;
}

s32 FUN_00000ade(u32 r6) {
    u32 r0 = (r6<<5)+1;
    FUN_00000bf0(r6, &DAT_0000134c);
    if (FUN_00000a48(DAT_00001351) <= 1) {
        FUN_00000bf0(r0, &DAT_0000134c);
        if (FUN_00000a48(DAT_00001351) <= 1) {
            return 0;
        }
    }
    return -1;
}

s32 FUN_00000b2e(u32 r6, u8 *r7) {
    DAT_00001360 = r7;
    CPU_IO.P51D = 0;
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0x00;
    CPU_IO.P24D = 0;
    CPU_IO.P25D = 1;
    NAND_FLASH_ADDRESS = 0x00;
    NAND_FLASH_ADDRESS = r6;
    NAND_FLASH_ADDRESS = r6>>8;
    NAND_FLASH_ADDRESS = r6>>16;
    CPU_IO.P25D = 0;
    if (FUN_00000a8e(600) == -1) {
        CPU_IO.P51D = 1;
        return -1;
    }
    // ECC circuit reset: Reset
    CPU_IO.ECCRST = 1;
    // ECC circuit enable: Enabled
    CPU_IO.ECCEN = 1;
    for (DAT_0000135c=0x200; DAT_0000135c!=0; DAT_0000135c--) {
        *DAT_00001360++ = NAND_FLASH_ADDRESS;
    }
    // ECC circuit enable: Disabled
    CPU_IO.ECCEN = 0;
    CPU_IO.P51D = 1;
    DAT_0000135c = 29999;
    // Parity data ready status == Busy
    while (CPU_IO.ECCRDY == 0) {
        DAT_0000135c--;
        if (DAT_0000135c == 0x00) {
            return -1;
        }
    }
    return 0;
}

s32 FUN_00000bf0(u32 r6, u8 *r7) {
    DAT_00001360 = r7;
    CPU_IO.P51D = 0;
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0x50;
    CPU_IO.P24D = 0;
    CPU_IO.P25D = 1;
    NAND_FLASH_ADDRESS = 0x00;
    NAND_FLASH_ADDRESS = r6;
    NAND_FLASH_ADDRESS = r6>>8;
    NAND_FLASH_ADDRESS = r6>>16;
    CPU_IO.P25D = 0;
    if (FUN_00000a8e(600) == -1) {
        CPU_IO.P51D = 1;
        return -1;
    }
    for (DAT_0000135c=0x10; DAT_0000135c!=0; DAT_0000135c--) {
        *DAT_00001360++ = NAND_FLASH_ADDRESS;
    }
    CPU_IO.P51D = 1;
    return 0;
}

u32 FUN_00000c7e(u32 r6) {
    DAT_000013e0 = 0;
    DAT_000013e8 = 0;
    DAT_000013e4 = 0;
    // ~r6: (h) abcdefgh ijklmnop qrstuvwx
    // DAT_000013dc = 00abcdef
    // DAT_000013dd = ijklmnop
    // DAT_000013de = qrstuvwx
    DAT_000013dc = ((~(r6>>16))&0xff)>>2;
    DAT_000013dd = ~(r6>>8);
    DAT_000013de = ~r6;
    for (DAT_000013d4=0; DAT_000013d4<2; DAT_000013d4++) {
        if (DAT_000013d4 != 0) {
            DAT_000013dd = DAT_000013de;
        }
        // DAT_000013e8 = ikmoqsuw
        // DAT_000013e4 = jlnprtvx
        s8 r7 = DAT_000013dd;
        for (DAT_000013d8=7; DAT_000013d8>=0; DAT_000013d8-=2) {
            s8 r0 = r7 >> (DAT_000013d8&0x1f);
            DAT_000013e8 = (r0&0x01)|(DAT_000013e8<<1);
            s8 r9 = r7 >> ((DAT_000013d8-1)&0x1f);
            DAT_000013e4 = (r9&0x01)|(DAT_000013e4<<1);
        }
        if (DAT_000013d4 != 0){
            DAT_000013d8 = 6;
        } else {
            DAT_000013d8 = 7;
        }
        // DAT_000013e0 = 0ace0bdf
        for (; DAT_000013d8 >= 0; DAT_000013d8-=2) {
            s8 r9 = DAT_000013dc >> (DAT_000013d8&0x1f);
            DAT_000013e0 |= (r9&0x01)|(DAT_000013e0<<1);
        }
    }
    DAT_000013e4 = DAT_000013e4&0xff;
    DAT_000013e8 = DAT_000013e8&0xff;
    DAT_000013e0 = DAT_000013e0&0xff;
    return (DAT_000013e0<<16) + (DAT_000013e8<<8) + DAT_000013e4;
}

s32 FUN_00000dfa(u32* r6, u32 r7, u32 r8) {
    u32 r1 = FUN_00000c7e(r7) | FUN_00000c7e(r8);
    DAT_000013fa = r1;
    DAT_000013fb = r1>>8;
    DAT_000013f8 = (r1>>16)&0x7;
    DAT_000013f9 = (r1>>20)&0x7;
    if (r1 != (~DAT_000013fb)&0xff) {
        return -1;
    }
    if (DAT_000013f8 == (~DAT_000013f9)&0x7) {
        DAT_000013f4 = DAT_000013fb + r6;
        *DAT_000013f4 |= 1<<DAT_000013f9;
        return 0;
    }
    return -1;
}

s32 FUN_00000e96() {
    u8 r6;
    DAT_000013b4 = 0x01;
    // Serial I/F Ch.2 SRDY selection: P24/TM2
    CPU_IO.SSRDY2 = 0;
    // P24 function selection: P24
    CPU_IO.CFP24 = 0;
    CPU_IO.P24D = 0;
    CPU_IO.IOC24 = 1;
    // Serial I/F Ch.2 SCLK selection: P25/TM3
    CPU_IO.SSCLK2 = 0;
    // P25 function selection: P25
    CPU_IO.CFP25 = 0;
    CPU_IO.P25D = 0;
    CPU_IO.IOC25 = 1;
    // Serial I/F Ch.2 SOUT selection: P26/TM4
    CPU_IO.SSOUT2 = 0;
    // P26 function selection: P26
    CPU_IO.CFP26 = 0;
    CPU_IO.P26D = 1;
    CPU_IO.IOC26 = 0;
    // P34 port extended function: #SMWE
    CPU_IO.EFP34 = 1;
    // P35 port extended function: #SMRE
    CPU_IO.EFP35 = 1;
    // Flash device mode: 8 bits
    CPU_IO.MODE = 0;
    // Areas 16–15 device size selection: 8 bits
    // Areas 16–15 output disable delay time: 0.5
    // Areas 16–15 wait control: 2
    CPU_IO.us_BCUAREA_A18_15 = 0x42;
    // P51 port extended function: P51
    CPU_IO.EFP51 = 1;
    CPU_IO.P51D = 0;
    CPU_IO.IOC51 = 1;
    // Serial I/F Ch.2 SIN selection: P27/TM5
    CPU_IO.SSIN2 = 0;
    // P27 function selection: P27
    CPU_IO.CFP27 = 0;
    CPU_IO.P27D = 0;
    CPU_IO.IOC27 = 1;
    // NAND flash I/F #CE area selection (according of CEFUNC): #CE5/#CE15(+16)
    CPU_IO.SMCES = 0;
    CPU_IO.P51D = 0;
    CPU_IO.P25D = 0;
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0xff;
    CPU_IO.P24D = 0;
    DAT_0000140c = 0x00;
    if (CPU_IO.P26D == 0) {
        do {
            DAT_0000140c++;
            if (DAT_0000140c > 35999) {
                break;
            }
        } while (CPU_IO.P26D == 0);
        DAT_0000140c = 0;
    }
    if (DAT_0000140c) {
        CPU_IO.P51D = 1;
        return -1;
    }
    CPU_IO.P24D = 1;
    NAND_FLASH_ADDRESS = 0x90;
    CPU_IO.P24D = 0;
    CPU_IO.P25D = 1;
    DAT_00001408 = NAND_FLASH_ADDRESS;
    DAT_00001409 = NAND_FLASH_ADDRESS;
    DAT_00001414 = NAND_FLASH_ADDRESS;
    DAT_00001415 = NAND_FLASH_ADDRESS;
    CPU_IO.P51D = 1;
    DAT_0000140c = 0x00;
    for (r6=0; r6<7; r6++) {
        if (DAT_00001278[r6].a == DAT_00001409) {
            DAT_00001410 = r6;
            DAT_0000140c = 0x00;
            break;
        }
    }
    if (DAT_0000140c) {
        return -1;
    }
    u8 *r5 = DAT_00001410*24;
    DAT_00001388 = DAT_00001278[DAT_00001410].b;
    DAT_0000138c = DAT_00001278[DAT_00001410].c;
    DAT_00001390 = DAT_00001278[DAT_00001410].d;
    DAT_00001394 = DAT_00001278[DAT_00001410].e;
    DAT_000013a4 = DAT_00001278[DAT_00001410].g;
    if ((DAT_00001408 == 0xec) || (DAT_00001408 == 0xad)) {
        DAT_00001404 = DAT_00001278[DAT_00001410].f;
    } else {
        DAT_00001404 = 0;
    }
    DAT_000013c4 = 0;
    DAT_000013c8 = 0x200;
    DAT_000013cc = DAT_00001394*DAT_0000138c;
    DAT_000013d0 = &DAT_00001320;
    if (DAT_00001388 == 0) {
        DAT_00001374 = FUN_00000b2e;
        DAT_0000137c = FUN_00000bf0;
        DAT_0000136c = FUN_00000ade;
    } else {
        DAT_00001374 = FUN_000008c6;
        DAT_0000137c = FUN_000009a2;
        DAT_0000136c = FUN_000007cc;
    }
    return 0;
}

void FUN_0000113c() {
    FUN_00000e96();
}

s32 FUN_00001144(u32 r6, u32 r7){
    for (DAT_0000140c=0; DAT_0000140c<3; DAT_0000140c++) {
        if (DAT_00001374(r6, r7) == -1) {
            return -1;
        }
        // Area 0 ECC line parity byte + (Area 0 column parity data)<<18
        DAT_00001418 = CPU_IO.LP0 + (CPU_IO.CP0<<16);
        // Area 1 ECC line parity byte + (Area 1 column parity data)<<18
        DAT_0000141c = CPU_IO.LP1 + (CPU_IO.CP1<<16);
        if (DAT_0000137c(r6, DAT_00001428) == -1) {
            return -1;
        }
        DAT_00001420 = (DAT_00001428[15]<<16) + (DAT_00001428[14]<<8) + DAT_00001428[13];
        DAT_00001424 = (DAT_00001428[10]<<16) + (DAT_00001428[9]<<8) + DAT_00001428[8];
        if (DAT_00001420 != DAT_00001418) {
            DAT_00001438 = FUN_00000dfa(r7, DAT_00001418, DAT_00001420);
        } else {
            DAT_00001438 = 0;
        }
        if (DAT_00001424 != DAT_0000141c) {
            DAT_0000143c = FUN_00000dfa(r7+0x100, DAT_0000141c, DAT_00001424);
        } else {
            DAT_0000143c = 0;
        }
        if (DAT_00001438 == 0 && DAT_0000143c == 0) {
            return 0;
        }
    }
    return -1;
}
